1. Field of the Invention
This invention relates generally to memory optimization in very large scale integrated circuit (VLSI) design and specifically to memory optimization in VLSI design using generic memory models.
2. Description of Related Art
Integrated circuits and their designs are getting more and more complex. A typical design cycle may last a year or more and costs millions of dollars. With a long and expensive design cycle, it is important to make appropriate choices for, among others, memory instances. It is not uncommon for advanced system-on-chip (SoC) designs to include over a thousand memory instances occupying up to half of the design's die area. The memory consumes a significant portion of the SoC's power and may limit the SoC's performance. Accordingly, optimizing memory performance in an SoC is becoming ever more important.
Memory selection typically occurs early in the SoC design process. The designer typically can choose from many different memories available from many different memory suppliers. With advances in process technology, memory suppliers are providing an increasing number of options and design choices to make power, performance, and area (PPA) trade-offs when selecting memories.
Once a memory instance is selected, it is instantiated in a register transfer level (RTL) description of the SoC design, which is used in the rest of the design flow for the integrated circuit design. However, after this point, it is more difficult to change the memory selection as it takes some time and effort to change the RTL description. The design flow is disrupted as the RTL description is modified, corresponding changes may have to be made in other descriptions or models, and later steps in the design flow may have to be repeated using the modified RTL. In addition, the modified RTL must be re-verified. Given this disruption, once a memory architecture is selected and coded into the RTL description, there is a disincentive to change this later during the design cycle. This can make it more difficult to take advantage of the increasing number of design choices provided by memory suppliers and silicon technologies. In addition, this can have a significant impact on the overall SoC performance, area, and power since memories account for a significant portion of an SoC design.